Re: [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask

[neil . armstrong]

On 02/02/2024 02:48, Mike Tipton wrote:
> The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
> target. Fix it.
>
> Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
> Signed-off-by: Mike Tipton <quic_mdtipton@xxxxxxxxxxx>
> ---
>   drivers/interconnect/qcom/sm8650.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
> index b83de54577b6..b962e6c233ef 100644
> --- a/drivers/interconnect/qcom/sm8650.c
> +++ b/drivers/interconnect/qcom/sm8650.c
> @@ -1160,7 +1160,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
>   
>   static struct qcom_icc_bcm bcm_acv = {
>   	.name = "ACV",
> -	.enable_mask = BIT(3),
> +	.enable_mask = BIT(0),
>   	.num_nodes = 1,
>   	.nodes = { &ebi },
>   };

Indeed it changed in the meantime


Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>