> > James Mastros wrote:
> > > Then again,
> > > if it deviates from the Intel chips on an undefined matter, or goes
above
> > > and beyond the call of duty, then the chip is better then the Intel
> > > "equivlent" in that respect, and we should take advantage of those
features
> > > as best as we can.
>
> > In this case, I think Cyrix did the right thing. They added a feature,
> > (powerdown the CPU as much as possible when not doing anything else).
> > Now they found out that the Intel specs (indirectly) say the TSC needs
> > to keep running. So... they made their feature an option. If your OS
> > isn't prepared to take the consequenses of the added feature, don't
> > turn it on. Simple.
>
> I hate to have to keep bringing this up: the Cyrix problem is not an
> 'added feature.' They destroy the top 32-bits of the TSC on HLT. We're
> not talking about "the TSC stops when the processor clock stops" which
is
> entirely valid (although also problematic for the kernel---this is
another
> issue entirely). To their credit, it appears that you can disable this
> behaviour. But there's no good reason for destroying register contents;
I
> find it very hard to call this a 'feature'.
I can't reproduce this on my 6x86MX rev.3. I think we have a
revision-limited bug here. The TSC *does* halt when SOH is enabled, but
the top bits are fine.
I previously posted a short C code that can test the TSC, could ppl. with
other revisions test their TSC and post results. (Make sure your machine
machine has been running a while so that the top word has a few ones in
it) I'll make it available soon at
http://www.ececs.uc.edu/~rreilova/6x86MX/test_cyrixTSC.c
-- Rafael
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu